This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

Book Information
ISBN 9781461408208
Author Konstantin Moiseev
Format Hardback
Page Count 233
Imprint Springer-Verlag New York Inc.
Publisher Springer-Verlag New York Inc.
Weight(grams) 5486g