Verification by Error Modeling: Using Testing Techniques in Hardware Verification by Katarzyna Radecka 9781441954022

Name: Verification by Error Modeling: Using Testing Techniques in Hardware Verification by Katarzyna Radecka 9781441954022
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This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

Book Information
ISBN 9781441954022
Author Katarzyna Radecka
Format Paperback
Page Count 216
Imprint Springer-Verlag New York Inc.
Publisher Springer-Verlag New York Inc.
Weight(grams) 367g

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