Description
This book focusses on the spacer engineering aspects of novel MOS-based device-circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
About the Author
Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal
Book Information
ISBN 9780367573553
Author Sudeb Dasgupta
Format Paperback
Page Count 138
Imprint CRC Press
Publisher Taylor & Francis Ltd
Weight(grams) 453g