Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent.Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography.This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.

Presents a precise understanding of various CMOS devices and the unprecedented etching issues encountered in the microelectronics industry

About the Author
Nicolas Posseme is a Senior Research Scientist in MIcrotechnologie & Nanotechnology and Deputy Head of Plasma Etching & Stripping in the Silicon Technologies division at the CEA-LETI Laboratory in Grenoble, France.


Book Information
ISBN 9781785480966
Author Nicolas Posseme
Format Hardback
Page Count 136
Imprint ISTE Press Ltd - Elsevier Inc
Publisher ISTE Press Ltd - Elsevier Inc
Weight(grams) 350g