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Formal Semantics and Proof Techniques for Optimizing VHDL Models by Kothanda Umamageswaran 9780792383758
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Formal Semantics and Proof Techniques for Optimizing VHDL Models by Kothanda Umamageswaran 9780792383758

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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Book Information
ISBN 9780792383758
Author Kothanda Umamageswaran
Format Hardback
Page Count 158
Imprint Springer
Publisher Springer
Weight(grams) 970g

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