This book covers the design applications of specific circuits and systems for accelerating neural network processing. Chapter 1 introduces neural networks and discusses its developmental history. Chapter 2 reviews Convolutional Neural Network model (CNN) and describes each layer function and example. Chapter 3 lists parallel architectures such as Intel CPU, Nvidia GPU, Google TPU and Microsoft NPU. Chapter 4 introduces a streaming graph for massive parallel computation through Blaize GSP and Graphcore IPU. Chapter 5 shows how to optimize convolution with UCLA's Deep Convolutional Neural Network (DCNN) accelerator filter decomposition and MIT's Eyeriss accelerator Row Stationary dataflow. Chapter 6 illustrates in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using Hybrid Memory Cube (HMC). Chapter 7 highlights near-memory architecture through the embedded eDRAM of Institute of Computing Technology (ICT), Chinese Academy of Science, DaDianNao supercomputer, and others. Chapter 8 describes how Stanford Energy Efficient Inference Engine, Institute of Computing Technology (ICT) and others handle network sparsity through network pruning. Chapter 9 introduces a 3D neural processing technique to support multiple layers neural network. It also offers network bridge to overcome power and thermal challenges as well as the memory bottleneck.

Book Information
ISBN 9781119810452
Author Albert (Chun-Chen) Liu
Format Hardback
Page Count 300
Imprint Wiley-Blackwell
Publisher John Wiley and Sons Ltd
Weight(grams) 666g